Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if
Clue is growing! We are now hiring a System Engineer ➪ About Clue At Clue, we research, design, and manufacture new computing technologies to enable innovative intelligent systems. Our motto is to create simple solutions to big
Bull is a story. One with a century of European innovation and a working environment where experts design powerful, sustainable, and sovereign digital solutions, enabling states and industries to retain full control over their data and
Experteer Overview Consulte la descripción del puesto a continuación. Si confía en que tiene las habilidades y la experiencia adecuadas, envíe su solicitud hoy mismo. In this role you will contribute to verifying complex ASICs using constraint-random,
Atos SE is seeking an Asic Verification Lead to verify complex ASIC architectures for high-end and exascale servers. ¿Tiene las habilidades necesarias para este puesto? Lea todos los detalles a continuación y presente su candidatura hoy mismo. The role
Atos SE is seeking an Asic Verification Lead to verify complex ASIC architectures for high-end and exascale servers. The role involves driving verification strategy and collaborating closely with design teams for reliable semiconductor designs.Applicants should have over 8 years of
Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. ¿Es usted el solicitante adecuado para esta oportunidad? Descúbralo leyendo el resumen del puesto a continuación. The role focuses on constraint-random,
Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. The role focuses on constraint-random, coverage-driven verification of complex ASICs such as network controllers and routers, using UVM, SystemVerilog and C++.You will collaborate
About SiPearl… SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy,
Digital Design Verification Engineer ¿Está pensando en solicitar este empleo? No se demore, desplácese hacia abajo y envíe su solicitud lo antes posible para no perder la oportunidad. Location: Valencia & Spain About the Role We are looking
Job Summary A Mixed-Signal Design & Verification Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure.
Digital Design Verification Engineer (Freelance / Remote) Location: Remote (Based in Spain) Project Type: Freelance / Contract Required Skills & Experience Proven hands-on experience in ASIC/FPGA digital design verification for complex mixed-signal or processor-based SoCs. Deep expertise in SystemVerilog and
GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution. ¿Tiene su CV preparado? Si es así y confía en que este es el puesto ideal para
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Puede obtener más detalles sobre la naturaleza de esta vacante y lo que se espera de los solicitantes leyendo la información a continuación. Overview At Akuaro, we
Are you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and… Sea uno de los primeros solicitantes, lea la descripción completa del puesto a continuación y luego
Monolithic Power Systems, Inc. Por favor, asegúrese de leer atentamente los siguientes detalles antes de enviar cualquier solicitud. is seeking a Mixed-Signal Design & Verification Lead in Barcelona, Spain. This role involves leading the MPS Mixed-Signal Design
This Full time on site position offers great opportunities for career growth. Siga leyendo para descubrir lo que necesitará para tener éxito en este puesto, incluyendo habilidades, cualificaciones y experiencia. Main function and scope: Own and
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Puede obtener más detalles sobre la naturaleza de esta vacante y lo que se espera de los solicitantes leyendo la información a continuación. Overview At Akuaro, we
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure.