Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if
Clue is growing! We are now hiring a System Engineer ➪ About Clue At Clue, we research, design, and manufacture new computing technologies to enable innovative intelligent systems. Our motto is to create simple solutions to big
Bull is a story. One with a century of European innovation and a working environment where experts design powerful, sustainable, and sovereign digital solutions, enabling states and industries to retain full control over their data and
Atos SE is seeking an Asic Verification Lead to verify complex ASIC architectures for high-end and exascale servers. The role involves driving verification strategy and collaborating closely with design teams for reliable semiconductor designs.Applicants should have over 8 years of
Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. ¿Es usted el solicitante adecuado para esta oportunidad? Descúbralo leyendo el resumen del puesto a continuación. The role focuses on constraint-random,
Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. The role focuses on constraint-random, coverage-driven verification of complex ASICs such as network controllers and routers, using UVM, SystemVerilog and C++.You will collaborate
Experteer Overview Consulte la descripción del puesto a continuación. Si confía en que tiene las habilidades y la experiencia adecuadas, envíe su solicitud hoy mismo. In this role you will contribute to verifying complex ASICs using constraint-random,
Atos SE is seeking an Asic Verification Lead to verify complex ASIC architectures for high-end and exascale servers. ¿Tiene las habilidades necesarias para este puesto? Lea todos los detalles a continuación y presente su candidatura hoy mismo. The role
About SiPearl… SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy,
Digital Design Verification Engineer ¿Está pensando en solicitar este empleo? No se demore, desplácese hacia abajo y envíe su solicitud lo antes posible para no perder la oportunidad. Location: Valencia & Spain About the Role We are looking
ASIC Design Engineer | Job DetailsAre you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and…We are expanding our teams in the GNSS-User Segment Navigation unit to take on
Job Summary A Mixed-Signal Design & Verification Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure.
This Full time on site position offers great opportunities for career growth.Main function and scope:Own and execute backend implementation flows for ASIC and/or FPGA designs.Perform logic synthesis, constraint development, optimization, and design quality checks.Run place and route
Digital Design Verification Engineer (Freelance / Remote) Location: Remote (Based in Spain) Project Type: Freelance / Contract Required Skills & Experience Proven hands-on experience in ASIC/FPGA digital design verification for complex mixed-signal or processor-based SoCs. Deep expertise in SystemVerilog and
Digital Design Verification Engineer (Freelance / Remote)Location: Remote (Based in Spain)Project Type: Freelance / ContractRequired Skills & ExperienceProven hands-on experience in ASIC/FPGA digital design verification for complex mixed-signal or processor-based SoCs.Deep expertise in SystemVerilog and UVM (Universal Verification Methodology) testbench development.Strong
Monolithic Power Systems, Inc. is seeking a Mixed-Signal Design & Verification Lead in Barcelona, Spain. This role involves leading the MPS Mixed-Signal Design team and developing frameworks for complex digital and mixed-signal ICs. Candidates should have extensive
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure.
Experteer Overview Si cree que es el candidato ideal para la siguiente oportunidad, envíe su solicitud después de leer la descripción completa. In this role you will contribute to digital design efforts for cutting-edge semiconductor technology.
Asic Verification Lead Por favor, presente su candidatura sin demora si su perfil encaja bien con este puesto, debido al alto nivel de interés. In this role, you will play a key part in verifying complex ASIC architectures used