Bull is seeking an experienced ASIC Verification Engineer to join our team in Madrid or remotely within Spain. ¿Es usted el solicitante adecuado para esta oportunidad? Descúbralo leyendo el resumen del puesto a continuación. The role focuses on
Asic Verification Lead Por favor, presente su candidatura sin demora si su perfil encaja bien con este puesto, debido al alto nivel de interés. In this role, you will play a key part in verifying complex ASIC architectures used
Atos SE is seeking an Asic Verification Lead to verify complex ASIC architectures for high-end and exascale servers. ¿Tiene las habilidades necesarias para este puesto? Lea todos los detalles a continuación y presente su candidatura hoy mismo. The role
Clue is growing! We are now hiring a System Engineer ➪ About Clue At Clue, we research, design, and manufacture new computing technologies to enable innovative intelligent systems. Our motto is to create simple solutions to
Company:Qualcomm Europe, Inc. Spain Branch Office Job Area:Engineering Group, Engineering Group Machine Learning Engineering General Summary: As a Senior Technical Standards contributor and participant, you will work closely with internal and external partners to improve and
Cis Electronics Engineering busca un Ingeniero de Verificación de Diseño Digital (Freelance / Remoto) para trabajar en proyectos de SoCs complejos. Se anima a todos los posibles solicitantes a que se desplacen y lean la descripción
Monolithic Power Systems, Inc. Asegúrese de que toda la información de su solicitud está actualizada y en orden antes de inscribirse en esta oportunidad. in Barcelona seeks a Digital Verification Intern to assist in validation, integration, simulation,
Digital Design Verification Engineer ¿Está pensando en solicitar este empleo? No se demore, desplácese hacia abajo y envíe su solicitud lo antes posible para no perder la oportunidad. Location: Valencia & Spain About the Role We are
Digital Design Verification Engineer (Freelance / Remote) Habilidades, experiencia, cualificaciones. Si tiene el perfil adecuado para esta oportunidad, asegúrese de inscribirse hoy mismo. Location: Remote (Based in Spain) Project Type: Freelance / Contract Required Skills & Experience
This Full time on site position offers great opportunities for career growth. Siga leyendo para descubrir lo que necesitará para tener éxito en este puesto, incluyendo habilidades, cualificaciones y experiencia. Main function and scope: Own and
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Puede obtener más detalles sobre la naturaleza de esta vacante y lo que se espera de los solicitantes leyendo la información a continuación. Overview At Akuaro,
Job Summary A Mixed-Signal Design & Verification Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital
ASIC Design Engineer | Job DetailsAre you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and…We are expanding our teams in the GNSS-User Segment Navigation unit to take
Are you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and… Sea uno de los primeros solicitantes, lea la descripción completa del puesto a continuación y luego
Overview In this role you will contribute to digital design efforts for cutting-edge semiconductor technology. You will work on advanced technology nodes and take ownership of RISC-V designs, CPU architecture components, PCIe protocols, and machine learning
Overview In this role you will contribute to receiver technology projects, focusing on migrating an architecture from Xilinx MPSoC/FPGA to an ASIC solution. You will shape the target ASIC architecture, implement RTL blocks, and optimize internal interfaces while
GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution. ¿Tiene su CV preparado? Si es así y confía en que este es el puesto ideal para
Monolithic Power Systems, Inc. Por favor, asegúrese de leer atentamente los siguientes detalles antes de enviar cualquier solicitud. is seeking a Mixed-Signal Design & Verification Lead in Barcelona, Spain. This role involves leading the MPS Mixed-Signal Design
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) Puede obtener más detalles sobre la naturaleza de esta vacante y lo que se espera de los solicitantes leyendo la información a continuación. Overview At Akuaro,