Atos SE is seeking an ASIC Verification Engineer to join their innovative team in Madrid or Barcelona, or to work remotely within Spain. Antes de solicitar este puesto, por favor, lea la siguiente información sobre esta oportunidad que encontrará
Photonic Sensors & Algorithms in Paterna, Spain, is seeking a Digital Design Verification Engineer to develop innovative low-power consumption ASICs that produce high-quality depth maps and images. The role includes defining efficient digital designs and collaborating with design engineers to
Dormont Manufacturing Co is seeking a Sr. DFT Engineer to lead the design and implementation of Digital and Mixed-Signal ICs DFT architectures. The ideal candidate should have extensive experience in RTL design and debugging, with excellent skills
Dormont Manufacturing Co is seeking a Sr. DFT Engineer to lead the design and implementation of Digital and Mixed-Signal ICs DFT architectures. The ideal candidate should have extensive experience in RTL design and debugging, with excellent skills
MonolithicPowerSystems,Inc.(MPS)isoneofthefastestgrowingcompaniesintheSemiconductorindustry.WeareworldwidetechnicalleadersinIntegratedPowerSemiconductorsandSystemsPowerdeliveryarchitectures.AtMPS,wecultivatecreativity,arepassionateaboutsustainability,andarecommittedtoprovidingleading-edgeproductsandinnovationtoourcustomers.Ourportfoliooftechnologyhelpspowerourworld—comejoinourteamandseehowYOUcanmakeadifference. La descripción completa del puesto cubre todas las habilidades asociadas, la experiencia previa y cualquier cualificación que se espera que tengan los solicitantes. Job Description: Job Summary: A Mixed-Signal Design & Verification Lead will lead, train
Experienced Verification Engineer to lead DV activities across customer projects, planning and executing SoC, ASIC, and IP verification. Collaborates with teams and customers to ensure high-quality outcomes and drive innovation....
Monolithic Power Systems, Inc. is seeking a Mixed-Signal Design & Verification Lead in Barcelona, Spain. This role involves leading the MPS Mixed-Signal Design team and developing frameworks for complex digital and mixed-signal ICs. Candidates should have extensive
Job Summary A Mixed-Signal Design & Verification Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs
Are you an experienced Verification Engineer looking for your next challenge? Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Verification Engineer. With design centers
Job Description A Sr./Staff Mixed‑Signal Design & Verification Engineer will lead the Mixed‑Signal Design and Verification tasks, environment and developments of complex mixed‑signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power
Overview Meet the Team Join the Physical Design CAD & Methodology Team - a technically strong group responsible for developing and supporting RTL-to-GDS Physical Design implementation and signoff flows across multiple ASIC programs. Our team works closely
Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/System Verilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital
Company Overview IDEADED is a Spanish deep-tech company with over 10 years of experience developing next-generation semiconductor technologies. We combine advanced research, design innovation, and process engineering to create solutions that go beyond traditional silicon and
Asic Verification Lead Por favor, asegúrese de leer completamente el resumen y los requisitos de esta oportunidad de empleo que se detallan a continuación. In this role, you will play a key part in verifying complex ASIC architectures used
Hireroo is seeking a Lead PCIe Engineer in Barcelona to define and integrate PCIe subsystems for advanced semiconductor solutions. This hybrid role involves close collaboration with architecture, RTL, verification, and physical design teams. Por favor, lea detenidamente la
GMV Spain is expanding its GNSS-User Segment Navigation unit and is looking for a graduate in Electronic Engineering, Telecommunications, or a similar field specializing in digital hardware programming. Para ser considerado para una entrevista, por favor,
Company Description Por favor, verifique que tiene el nivel de experiencia y las cualificaciones adecuadas leyendo la descripción completa de esta oportunidad a continuación. IDEADED is a Spanish deep-tech company with over 10 years of experience
Meet the Team Se anima a todos los posibles solicitantes a que se desplacen y lean la descripción completa del puesto antes de presentar su candidatura. Join the Physical Design CAD & Methodology Team—a technically strong
Overview Asegúrese de presentar su candidatura con toda la información solicitada, tal como se expone en la descripción del puesto a continuación. Meet the Team Join the Physical Design CAD & Methodology Team—a technically strong group
Meet the Team Join the Physical Design CAD & Methodology Team—a technically strong group responsible for developing and supporting RTL-to-GDS Physical Design implementation and signoff flows across multiple ASIC programs. Our team works closely with Physical Design,